The present invention relates to arrays for performing logic functions and more particularly it is related to the manufacture of PLA chips with different circuit configurations.
The performing of logic in an array of identical circuit elements each located at a unique intersection of an input and output line in a grid of intersecting input and output lines is well known. It is also well known to perform logic in a compound arrangement of these arrays called a programmable logic array chip (PLA) by using the outputs of one array as the inputs to another array. Co-pending application Ser. No. 537,219 filed on Dec. 30, 1974 describes such a PLA on which a number of decoders feed inputs to a first array called a product term generator or an AND array which in turn supplies outputs to a second array called a sum of product term generator or an OR array. The outputs of the OR array are then used to control the setting and resetting of a string of latches so that both combinatorial and sequential logic functions can be performed by the PLA. The particular logic functions actually performed by the given PLA are controlled by the locations and number of the active logic circuits in the AND and OR arrays of the PLA and also by how inputs are supplied to the decoders either from off the chip or from the latches. Furthermore, the type of latch used determines the logic functions performed on the PLA chip. Therefore, it is important that a number of different types of latches be available on the PLA chip each in the quantities needed to permit the efficient use of the chip.